Chenlei Hu 442398bb9f Port SDForge's preprocessor structure (#2754) ... * wip * wip2 * wip3 * fix issues * Add scribble xdog * port legacy processors * nit * Add tests * Fix modules test * Add back normal_dsine * Remove legacy code * Remove code * Add tests * rename param * Linter ignore * fix is_image * fix is_image * nit * nit * Better assertion message * Add back ip-adapter-auto * Add test * Fix various tag matching * fix * Add back preprocessor cache * Add back sparse ctrl * fix test failure * Add log		2024-04-17 22:28:56 -04:00
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__init__.py	Multi-ControlNet Batch (#683)	2023-04-23 16:35:31 -04:00
batch_hijack_test.py	🔧 Support SDXL in tests (#2254)	2023-11-12 14:12:54 -05:00
cn_script_test.py	Port SDForge's preprocessor structure (#2754)	2024-04-17 22:28:56 -04:00
infotext_test.py	🐛 Fix infotext advanced weighting (#2408)	2024-01-04 17:02:44 -05:00
utils_test.py	🔧 Support SDXL in tests (#2254)	2023-11-12 14:12:54 -05:00