mirror of https://github.com/vladmandic/automatic
168 lines
6.4 KiB
Python
168 lines
6.4 KiB
Python
"""
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Modified from Triton MatMul example.
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PyTorch torch._int_mm is broken on backward pass with Nvidia, so we use Triton on the backward pass with Nvidia.
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AMD RDNA2 doesn't support torch._int_mm as it requires INT8 WMMA, so we use INT8 DP4A via Triton.
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PyTorch doesn't support FP32 output type with FP16 MM, so we use Triton for FP16 MM too.
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matmul_configs we use takes AMD and Intel into consideration too.
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SDNQ Triton configs can outperform RocBLAS and OneDNN.
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"""
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import torch
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import triton
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import triton.language as tl
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matmul_configs = [
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triton.Config({'BLOCK_SIZE_M': BM, 'BLOCK_SIZE_N': BN, "BLOCK_SIZE_K": BK, "GROUP_SIZE_M": GM}, num_warps=w, num_stages=s)
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for BM in [32, 64, 128, 256]
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for BN in [32, 64, 128, 256]
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for BK in [32, 64, 128]
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for GM in [8, 16]
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for w in [8, 16]
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for s in [2]
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]
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@triton.autotune(configs=matmul_configs, key=["M", "N", "K", "stride_bk", "ACCUMULATOR_DTYPE"], cache_results=True)
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@triton.jit
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def triton_mm_kernel(
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a_ptr, b_ptr, c_ptr,
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M: int, N: int, K: int,
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stride_am: int, stride_ak: int,
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stride_bk: int, stride_bn: int,
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stride_cm: int, stride_cn: int,
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ACCUMULATOR_DTYPE: tl.constexpr,
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BLOCK_SIZE_M: tl.constexpr,
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BLOCK_SIZE_N: tl.constexpr,
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BLOCK_SIZE_K: tl.constexpr,
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GROUP_SIZE_M: tl.constexpr,
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):
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pid = tl.program_id(axis=0)
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num_pid_m = tl.cdiv(M, BLOCK_SIZE_M)
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num_pid_n = tl.cdiv(N, BLOCK_SIZE_N)
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num_pid_in_group = GROUP_SIZE_M * num_pid_n
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group_id = pid // num_pid_in_group
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first_pid_m = group_id * GROUP_SIZE_M
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group_size_m = min(num_pid_m - first_pid_m, GROUP_SIZE_M)
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pid_m = first_pid_m + ((pid % num_pid_in_group) % group_size_m)
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pid_n = (pid % num_pid_in_group) // group_size_m
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tl.assume(pid_m >= 0)
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tl.assume(pid_n >= 0)
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tl.assume(stride_am > 0)
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tl.assume(stride_ak > 0)
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tl.assume(stride_bn > 0)
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tl.assume(stride_bk > 0)
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tl.assume(stride_cm > 0)
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tl.assume(stride_cn > 0)
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offs_am = (pid_m * BLOCK_SIZE_M + tl.arange(0, BLOCK_SIZE_M)) % M
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offs_bn = (pid_n * BLOCK_SIZE_N + tl.arange(0, BLOCK_SIZE_N)) % N
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offs_k = tl.arange(0, BLOCK_SIZE_K)
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a_ptrs = a_ptr + (offs_am[:, None] * stride_am + offs_k[None, :] * stride_ak)
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b_ptrs = b_ptr + (offs_k[:, None] * stride_bk + offs_bn[None, :] * stride_bn)
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accumulator = tl.zeros((BLOCK_SIZE_M, BLOCK_SIZE_N), dtype=ACCUMULATOR_DTYPE)
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for k in range(0, tl.cdiv(K, BLOCK_SIZE_K)):
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a = tl.load(a_ptrs, mask=offs_k[None, :] < K - k * BLOCK_SIZE_K, other=0.0)
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b = tl.load(b_ptrs, mask=offs_k[:, None] < K - k * BLOCK_SIZE_K, other=0.0)
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accumulator = tl.dot(a, b, accumulator, out_dtype=ACCUMULATOR_DTYPE)
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a_ptrs += BLOCK_SIZE_K * stride_ak
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b_ptrs += BLOCK_SIZE_K * stride_bk
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offs_cm = pid_m * BLOCK_SIZE_M + tl.arange(0, BLOCK_SIZE_M)
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offs_cn = pid_n * BLOCK_SIZE_N + tl.arange(0, BLOCK_SIZE_N)
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c_ptrs = c_ptr + stride_cm * offs_cm[:, None] + stride_cn * offs_cn[None, :]
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c_mask = (offs_cm[:, None] < M) & (offs_cn[None, :] < N)
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tl.store(c_ptrs, accumulator, mask=c_mask)
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# Intel requires tensor descriptors to perform good
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@triton.autotune(configs=matmul_configs, key=["M", "N", "K", "stride_bk", "ACCUMULATOR_DTYPE"], cache_results=True)
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@triton.jit
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def triton_mm_td_kernel(
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a_ptr, b_ptr, c_ptr,
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M: int, N: int, K: int,
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stride_am: int, stride_ak: int,
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stride_bk: int, stride_bn: int,
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stride_cm: int, stride_cn: int,
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ACCUMULATOR_DTYPE: tl.constexpr,
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BLOCK_SIZE_M: tl.constexpr,
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BLOCK_SIZE_N: tl.constexpr,
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BLOCK_SIZE_K: tl.constexpr,
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GROUP_SIZE_M: tl.constexpr,
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):
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pid = tl.program_id(axis=0)
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num_pid_m = tl.cdiv(M, BLOCK_SIZE_M)
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num_pid_n = tl.cdiv(N, BLOCK_SIZE_N)
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num_pid_in_group = GROUP_SIZE_M * num_pid_n
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group_id = pid // num_pid_in_group
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first_pid_m = group_id * GROUP_SIZE_M
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group_size_m = min(num_pid_m - first_pid_m, GROUP_SIZE_M)
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pid_m = first_pid_m + ((pid % num_pid_in_group) % group_size_m)
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pid_n = (pid % num_pid_in_group) // group_size_m
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tl.assume(pid_m >= 0)
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tl.assume(pid_n >= 0)
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tl.assume(stride_am > 0)
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tl.assume(stride_ak > 0)
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tl.assume(stride_bn > 0)
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tl.assume(stride_bk > 0)
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tl.assume(stride_cm > 0)
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tl.assume(stride_cn > 0)
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a_desc = tl.make_tensor_descriptor(base=a_ptr, shape=(M, K), strides=(stride_am, stride_ak), block_shape=(BLOCK_SIZE_M, BLOCK_SIZE_K))
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b_desc = tl.make_tensor_descriptor(base=b_ptr, shape=(K, N), strides=(stride_bk, stride_bn), block_shape=(BLOCK_SIZE_K, BLOCK_SIZE_N))
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off_k = 0
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accumulator = tl.zeros((BLOCK_SIZE_M, BLOCK_SIZE_N), dtype=ACCUMULATOR_DTYPE)
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for k in range(0, tl.cdiv(K, BLOCK_SIZE_K)):
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a = a_desc.load([pid_m * BLOCK_SIZE_M, off_k])
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b = b_desc.load([off_k, pid_n * BLOCK_SIZE_N])
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accumulator = tl.dot(a, b, accumulator, out_dtype=ACCUMULATOR_DTYPE)
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off_k += BLOCK_SIZE_K
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c_desc = tl.make_tensor_descriptor(base=c_ptr, shape=(M, N), strides=(stride_cm, stride_cn), block_shape=(BLOCK_SIZE_M, BLOCK_SIZE_N))
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c_desc.store([pid_m * BLOCK_SIZE_M, pid_n * BLOCK_SIZE_N], accumulator)
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def int_mm(a: torch.Tensor, b: torch.Tensor) -> torch.Tensor:
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assert a.shape[1] == b.shape[0], "Incompatible dimensions"
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assert a.is_contiguous(), "Matrix A must be contiguous"
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M, K = a.shape
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K, N = b.shape
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c = torch.empty((M, N), device=a.device, dtype=torch.int32)
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def grid(META):
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return (triton.cdiv(M, META["BLOCK_SIZE_M"]) * triton.cdiv(N, META["BLOCK_SIZE_N"]), )
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mm_kernel_func = triton_mm_td_kernel if b.is_contiguous() else triton_mm_kernel
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mm_kernel_func[grid](
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a, b, c,
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M, N, K,
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a.stride(0), a.stride(1),
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b.stride(0), b.stride(1),
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c.stride(0), c.stride(1),
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tl.int32,
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)
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return c
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def fp_mm(a: torch.FloatTensor, b: torch.FloatTensor) -> torch.FloatTensor:
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assert a.shape[1] == b.shape[0], "Incompatible dimensions"
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assert a.is_contiguous(), "Matrix A must be contiguous"
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M, K = a.shape
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K, N = b.shape
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c = torch.empty((M, N), device=a.device, dtype=torch.float32)
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def grid(META):
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return (triton.cdiv(M, META["BLOCK_SIZE_M"]) * triton.cdiv(N, META["BLOCK_SIZE_N"]), )
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mm_kernel_func = triton_mm_td_kernel if b.is_contiguous() else triton_mm_kernel
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mm_kernel_func[grid](
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a, b, c,
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M, N, K,
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a.stride(0), a.stride(1),
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b.stride(0), b.stride(1),
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c.stride(0), c.stride(1),
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tl.float32,
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)
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return c
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