mirror of https://github.com/vladmandic/automatic
code quality and layout fixes
parent
01d53edb25
commit
d2a47ee0ed
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@ -1,6 +1,5 @@
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from typing import Dict, Any, List, Tuple
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from typing import Dict, Any, List, Tuple
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# --- General MIOpen/rocBLAS variables (dropdown/textbox/checkbox) ---
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GENERAL_VARS: Dict[str, Dict[str, Any]] = {
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GENERAL_VARS: Dict[str, Dict[str, Any]] = {
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"MIOPEN_SYSTEM_DB_PATH": {
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"MIOPEN_SYSTEM_DB_PATH": {
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"default": "{VIRTUAL_ENV}\\Lib\\site-packages\\_rocm_sdk_devel\\bin\\",
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"default": "{VIRTUAL_ENV}\\Lib\\site-packages\\_rocm_sdk_devel\\bin\\",
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@ -16,7 +15,6 @@ GENERAL_VARS: Dict[str, Dict[str, Any]] = {
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"options": None,
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"options": None,
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"restart_required": True,
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"restart_required": True,
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},
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},
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# -- GEMM backend selector + companion toggles --------------------------
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"MIOPEN_GEMM_ENFORCE_BACKEND": {
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"MIOPEN_GEMM_ENFORCE_BACKEND": {
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"default": "1",
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"default": "1",
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"desc": "GEMM backend",
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"desc": "GEMM backend",
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@ -26,26 +24,25 @@ GENERAL_VARS: Dict[str, Dict[str, Any]] = {
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},
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},
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"PYTORCH_ROCM_USE_ROCBLAS": {
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"PYTORCH_ROCM_USE_ROCBLAS": {
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"default": "0",
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"default": "0",
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"desc": "PyTorch: Use rocBLAS.",
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"desc": "PyTorch: Use rocBLAS",
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"widget": "dropdown",
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"widget": "dropdown",
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"options": [("0 - Off", "0"), ("1 - On", "1")],
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"options": [("0 - Off", "0"), ("1 - On", "1")],
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"restart_required": True,
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"restart_required": True,
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},
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},
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"PYTORCH_HIPBLASLT_DISABLE": {
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"PYTORCH_HIPBLASLT_DISABLE": {
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"default": "1",
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"default": "1",
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"desc": "PyTorch: Use hipBLASLt.",
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"desc": "PyTorch: Use hipBLASLt",
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"widget": "dropdown",
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"widget": "dropdown",
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"options": [("0 - Allow hipBLASLt", "0"), ("1 - Disable hipBLASLt", "1")],
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"options": [("0 - Allow hipBLASLt", "0"), ("1 - Disable hipBLASLt", "1")],
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"restart_required": True,
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"restart_required": True,
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},
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},
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"ROCBLAS_USE_HIPBLASLT": {
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"ROCBLAS_USE_HIPBLASLT": {
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"default": "0",
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"default": "0",
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"desc": "rocBLAS: use hipBLASLt backend.",
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"desc": "rocBLAS: use hipBLASLt backend",
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"widget": "dropdown",
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"widget": "dropdown",
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"options": [("0 - Tensile (rocBLAS)", "0"), ("1 - hipBLASLt", "1")],
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"options": [("0 - Tensile (rocBLAS)", "0"), ("1 - hipBLASLt", "1")],
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"restart_required": True,
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"restart_required": True,
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},
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},
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# -- MIOpen behavioural settings ----------------------------------------
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"MIOPEN_FIND_MODE": {
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"MIOPEN_FIND_MODE": {
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"default": "2",
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"default": "2",
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"desc": "MIOpen Find Mode",
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"desc": "MIOpen Find Mode",
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@ -74,9 +71,6 @@ GENERAL_VARS: Dict[str, Dict[str, Any]] = {
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"options": [("0 - Off", "0"), ("1 - On", "1")],
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"options": [("0 - Off", "0"), ("1 - On", "1")],
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"restart_required": False,
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"restart_required": False,
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},
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},
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# -- Paths / sizes ------------------------------------------------------
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"MIOPEN_CONVOLUTION_MAX_WORKSPACE": {
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"MIOPEN_CONVOLUTION_MAX_WORKSPACE": {
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"default": "1073741824",
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"default": "1073741824",
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"desc": "MIOpen convolutions: max workspace (bytes; 1 GB)",
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"desc": "MIOpen convolutions: max workspace (bytes; 1 GB)",
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@ -99,7 +93,6 @@ GENERAL_VARS: Dict[str, Dict[str, Any]] = {
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"restart_required": False,
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"restart_required": False,
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},
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},
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# -- rocBLAS settings ---------------------------------------------------
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"ROCBLAS_STREAM_ORDER_ALLOC": {
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"ROCBLAS_STREAM_ORDER_ALLOC": {
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"default": "1",
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"default": "1",
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"desc": "rocBLAS stream-ordered memory allocation",
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"desc": "rocBLAS stream-ordered memory allocation",
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@ -128,8 +121,6 @@ GENERAL_VARS: Dict[str, Dict[str, Any]] = {
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"options": [("0 - Use Cache", "0"), ("1 - Benchmark new shapes", "1")],
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"options": [("0 - Use Cache", "0"), ("1 - Benchmark new shapes", "1")],
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"restart_required": False,
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"restart_required": False,
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},
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},
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# -- hipBLASLt settings -------------------------------------------------
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"PYTORCH_TUNABLEOP_HIPBLASLT_ENABLED": {
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"PYTORCH_TUNABLEOP_HIPBLASLT_ENABLED": {
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"default": "0",
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"default": "0",
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"desc": "TunableOp: benchmark hipBLASLt kernels",
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"desc": "TunableOp: benchmark hipBLASLt kernels",
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@ -137,8 +128,6 @@ GENERAL_VARS: Dict[str, Dict[str, Any]] = {
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"options": [("0 - Off", "0"), ("1 - On", "1")],
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"options": [("0 - Off", "0"), ("1 - On", "1")],
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"restart_required": False,
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"restart_required": False,
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},
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},
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# -- Logging: MIOpen -> rocBLAS -> hipBLASLt -----------------------------
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"MIOPEN_LOG_LEVEL": {
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"MIOPEN_LOG_LEVEL": {
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"default": "0",
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"default": "0",
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"desc": "MIOpen log verbosity level",
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"desc": "MIOpen log verbosity level",
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@ -169,14 +158,6 @@ GENERAL_VARS: Dict[str, Dict[str, Any]] = {
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},
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},
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}
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}
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# --- Solver toggles (inference/FWD only, RDNA2/3/4 compatible) ---
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# Removed entirely - not representable in the UI, cannot be set by users:
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# WRW (weight-gradient) and BWD (data-gradient) - training passes only, never run during inference
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# XDLOPS/CK CDNA-exclusive (MI100/MI200/MI300 matrix engine variants) - not on any RDNA
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# Fixed-geometry (5x10, 7x7-ImageNet, 11x11) - shapes never appear in SD/video inference
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# FP32-reference (NAIVE_CONV_FWD, FWDGEN) - IsApplicable() unreliable for FP16/BF16
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# Wide MPASS (F3x4..F7x3) - kernel sizes that cannot match any SD convolution shape
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# Disabled by default (added but off): RDNA3/4-only - Group Conv XDLOPS, CK default kernels
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_SOLVER_DESCS: Dict[str, str] = {}
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_SOLVER_DESCS: Dict[str, str] = {}
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_SOLVER_DESCS.update({
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_SOLVER_DESCS.update({
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@ -199,7 +180,7 @@ _SOLVER_DESCS.update({
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"MIOPEN_DEBUG_ATTN_SOFTMAX": "Enable Attention Softmax",
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"MIOPEN_DEBUG_ATTN_SOFTMAX": "Enable Attention Softmax",
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})
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})
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_SOLVER_DESCS.update({
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_SOLVER_DESCS.update({
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# Direct ASM - FWD inference only (WRW, fixed-geometry, FP32-reference removed)
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# Direct ASM — FWD inference only (WRW, fixed-geometry, FP32-reference removed)
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"MIOPEN_DEBUG_CONV_DIRECT_ASM_3X3U": "Enable Direct ASM 3x3U",
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"MIOPEN_DEBUG_CONV_DIRECT_ASM_3X3U": "Enable Direct ASM 3x3U",
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"MIOPEN_DEBUG_CONV_DIRECT_ASM_1X1U": "Enable Direct ASM 1x1U",
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"MIOPEN_DEBUG_CONV_DIRECT_ASM_1X1U": "Enable Direct ASM 1x1U",
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"MIOPEN_DEBUG_CONV_DIRECT_ASM_1X1UV2": "Enable Direct ASM 1x1UV2",
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"MIOPEN_DEBUG_CONV_DIRECT_ASM_1X1UV2": "Enable Direct ASM 1x1UV2",
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@ -207,12 +188,12 @@ _SOLVER_DESCS.update({
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"MIOPEN_DEBUG_CONV_DIRECT_ASM_1X1U_AI_HEUR": "Enable Direct ASM 1x1U AI Heuristic",
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"MIOPEN_DEBUG_CONV_DIRECT_ASM_1X1U_AI_HEUR": "Enable Direct ASM 1x1U AI Heuristic",
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})
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})
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_SOLVER_DESCS.update({
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_SOLVER_DESCS.update({
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# Direct OCL - FWD inference only (WRW, FWD11X11 fixed-geom, FWDGEN FP32-ref removed)
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# Direct OCL — FWD inference only (WRW, FWD11X11 fixed-geom, FWDGEN FP32-ref removed)
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"MIOPEN_DEBUG_CONV_DIRECT_OCL_FWD": "Enable Direct OCL FWD",
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"MIOPEN_DEBUG_CONV_DIRECT_OCL_FWD": "Enable Direct OCL FWD",
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"MIOPEN_DEBUG_CONV_DIRECT_OCL_FWD1X1": "Enable Direct OCL FWD1X1",
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"MIOPEN_DEBUG_CONV_DIRECT_OCL_FWD1X1": "Enable Direct OCL FWD1X1",
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})
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})
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_SOLVER_DESCS.update({
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_SOLVER_DESCS.update({
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# Winograd FWD - WRW removed; Fury/Rage kept as RDNA3/4 inference (off by default)
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# Winograd FWD — WRW removed; Fury/Rage kept as RDNA3/4 inference (off by default)
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"MIOPEN_DEBUG_AMD_WINOGRAD_3X3": "Enable AMD Winograd 3x3",
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"MIOPEN_DEBUG_AMD_WINOGRAD_3X3": "Enable AMD Winograd 3x3",
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"MIOPEN_DEBUG_AMD_WINOGRAD_RXS": "Enable AMD Winograd RxS",
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"MIOPEN_DEBUG_AMD_WINOGRAD_RXS": "Enable AMD Winograd RxS",
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"MIOPEN_DEBUG_AMD_WINOGRAD_RXS_FWD_BWD": "Enable AMD Winograd RxS FWD",
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"MIOPEN_DEBUG_AMD_WINOGRAD_RXS_FWD_BWD": "Enable AMD Winograd RxS FWD",
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"MIOPEN_DEBUG_AMD_WINOGRAD_RAGE_RXS_F2X3": "Enable AMD Winograd Rage RxS F2x3",
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"MIOPEN_DEBUG_AMD_WINOGRAD_RAGE_RXS_F2X3": "Enable AMD Winograd Rage RxS F2x3",
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})
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})
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_SOLVER_DESCS.update({
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_SOLVER_DESCS.update({
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# Multi-pass Winograd - only F3x2/F3x3 match typical 3x3 SD shapes; wider kernels removed
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# Multi-pass Winograd — only F3x2/F3x3 match typical 3x3 SD shapes; wider kernels removed
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"MIOPEN_DEBUG_AMD_WINOGRAD_MPASS_F3X2": "Enable AMD Winograd MPASS F3x2",
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"MIOPEN_DEBUG_AMD_WINOGRAD_MPASS_F3X2": "Enable AMD Winograd MPASS F3x2",
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"MIOPEN_DEBUG_AMD_WINOGRAD_MPASS_F3X3": "Enable AMD Winograd MPASS F3x3",
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"MIOPEN_DEBUG_AMD_WINOGRAD_MPASS_F3X3": "Enable AMD Winograd MPASS F3x3",
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})
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})
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_SOLVER_DESCS.update({
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_SOLVER_DESCS.update({
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# Implicit GEMM FWD - BWD/WRW (training), CDNA-exclusive XDLOPS variants removed
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# Implicit GEMM FWD — BWD/WRW (training), CDNA-exclusive XDLOPS variants removed
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"MIOPEN_DEBUG_CONV_IMPLICIT_GEMM_ASM_FWD_V4R1": "Enable ASM Implicit GEMM FWD V4R1",
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"MIOPEN_DEBUG_CONV_IMPLICIT_GEMM_ASM_FWD_V4R1": "Enable ASM Implicit GEMM FWD V4R1",
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"MIOPEN_DEBUG_CONV_IMPLICIT_GEMM_ASM_FWD_V4R1_1X1": "Enable ASM Implicit GEMM FWD V4R1 1x1",
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"MIOPEN_DEBUG_CONV_IMPLICIT_GEMM_ASM_FWD_V4R1_1X1": "Enable ASM Implicit GEMM FWD V4R1 1x1",
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"MIOPEN_DEBUG_CONV_IMPLICIT_GEMM_HIP_FWD_V4R1": "Enable HIP Implicit GEMM FWD V4R1",
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"MIOPEN_DEBUG_CONV_IMPLICIT_GEMM_HIP_FWD_V4R1": "Enable HIP Implicit GEMM FWD V4R1",
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"MIOPEN_DEBUG_CONV_IMPLICIT_GEMM_HIP_FWD_V4R4": "Enable HIP Implicit GEMM FWD V4R4",
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"MIOPEN_DEBUG_CONV_IMPLICIT_GEMM_HIP_FWD_V4R4": "Enable HIP Implicit GEMM FWD V4R4",
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})
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})
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_SOLVER_DESCS.update({
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_SOLVER_DESCS.update({
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# Group Conv XDLOPS FWD - RDNA3/4 (gfx1100+) only; disabled by default
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# Group Conv XDLOPS FWD — RDNA3/4 (gfx1100+) only; disabled by default
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"MIOPEN_DEBUG_GROUP_CONV_IMPLICIT_GEMM_HIP_FWD_XDLOPS": "Enable Group Conv Implicit GEMM XDLOPS FWD",
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"MIOPEN_DEBUG_GROUP_CONV_IMPLICIT_GEMM_HIP_FWD_XDLOPS": "Enable Group Conv Implicit GEMM XDLOPS FWD",
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"MIOPEN_DEBUG_GROUP_CONV_IMPLICIT_GEMM_HIP_FWD_XDLOPS_AI_HEUR": "Enable Group Conv Implicit GEMM XDLOPS FWD AI Heuristic",
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"MIOPEN_DEBUG_GROUP_CONV_IMPLICIT_GEMM_HIP_FWD_XDLOPS_AI_HEUR": "Enable Group Conv Implicit GEMM XDLOPS FWD AI Heuristic",
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# CK (Composable Kernel) default kernels - RDNA3/4 (gfx1100+); disabled by default
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# CK (Composable Kernel) default kernels — RDNA3/4 (gfx1100+); disabled by default
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"MIOPEN_DEBUG_CK_DEFAULT_KERNELS": "Enable CK (Composable Kernel) default kernels",
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"MIOPEN_DEBUG_CK_DEFAULT_KERNELS": "Enable CK (Composable Kernel) default kernels",
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})
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})
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# Solvers still in the registry but disabled by default.
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# Solvers still in the registry but disabled by default.
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# FORCE_IMMED_MODE_FALLBACK - overrides FIND_MODE entirely, defeats tuning DB
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# FORCE_IMMED_MODE_FALLBACK — overrides FIND_MODE entirely, defeats tuning DB
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# Fury RxS F2x3/F3x2 - RDNA3/4-only; harmless on RDNA2 but won't select
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# Fury RxS F2x3/F3x2 — RDNA3/4-only; harmless on RDNA2 but won't select
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# Rage RxS F2x3 - RDNA4-only
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# Rage RxS F2x3 — RDNA4-only
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# Group Conv XDLOPS - RDNA3/4-only (gfx1100+)
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# Group Conv XDLOPS — RDNA3/4-only (gfx1100+)
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# CK_DEFAULT_KERNELS - RDNA3/4-only (gfx1100+)
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# CK_DEFAULT_KERNELS — RDNA3/4-only (gfx1100+)
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SOLVER_DISABLED_BY_DEFAULT = {
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SOLVER_DISABLED_BY_DEFAULT = {
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"MIOPEN_DEBUG_FORCE_IMMED_MODE_FALLBACK",
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"MIOPEN_DEBUG_FORCE_IMMED_MODE_FALLBACK",
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"MIOPEN_DEBUG_AMD_WINOGRAD_FURY_RXS_F2X3",
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"MIOPEN_DEBUG_AMD_WINOGRAD_FURY_RXS_F2X3",
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